Exemplary embodiments relate to a block decoder of a semiconductor memory device and, more particularly, to a block decoder of a semiconductor memory device.
Recently, there is an increasing demand for semiconductor memory devices which can be electrically programmed and erased and which do not require the refresh function of rewriting data at specific intervals. In order to develop high-capacity memory devices capable of storing a large amount of data, research is being done on technologies for improving the degree of integration of memory devices. To this end, active research is being carried out on flash memory.
Flash memory is chiefly divided into NAND type flash memory and NOR type flash memory. The NOR type flash memory has an excellent random access time characteristic because memory cells are independently coupled to bit lines and word lines. The NAND type flash memory is excellent in terms of the degree of integration because a plurality of memory cells is coupled together in series and so each cell string requires, for example, only one contact. Accordingly, the NAND type flash memory may be used in high integration nonvolatile memory.
In general, a flash memory device includes a block decoder for selecting a memory cell array on a block basis in order to perform a program, a read, and an erase operations.
FIG. 1 is a diagram showing the arrangement of signal lines used in a block decoder circuit.
Referring to FIG. 1, a plurality of metal lines for receiving signals to control a block decoder is arranged on the side of a plurality of memory blocks (for example, 4096 memory blocks). For example, 32 metal lines XA<7;0>, XB<7;0>, XC<7;0>, and XD<7;0> are used to receive address signals to select a memory block. Here, assuming that the line width of each of the metal lines XA<7;0>, XB<7;0>, XC<7;0>, and XD<7;0> is 0.5 μm and the interval between the metal lines is 0.5 μm, a total of 32 μm space is required.